Honeywell ASIC/FPGA Engineer in Brno, Czech Republic
Innovate to solve the world's most important challenges
The ASIC team is a part of global ASC/FPGA organization in Honeywell being responsible for project execution, design and verification of safety critical designs for FPGAs.
- Translation of system level requirements into hardware
- Architecture definition of complex high speed ASIC/FPGAs
- Implementation of approved design in VHDL, Verilog or SystemVerilog
- Verification in simulation environment based on BFMs (VHDL) or UVM methodology (SystemVerilog)
- Generation of associated supporting documentation
Regular and frequent communication with chip project lead engineer
15 Build Requirements
25 Design and Simulation
25 Conduct Code Synthesis
25 Integration and Test Support
10 Prepare Documentation
Minimum of Bachelors Degree in Electrical Engineering or Computer Science
- Understanding of ASIC or FPGA development process.
- Experience with VHDL or Verilog for Xilinx, Actel or Altera devices. SystemVerilog is a plus.
- Knowledge of AMBA, PCI, Ethernet, I2C, SPI, OS Linux.
- Scripting language Perl, Shell, TCL or Python is a plus.
- Experience with ModelSim or other simulation tool
- Advanced knowledge of English
Exempt Celebrating 100 Years In Aviation
- Some Travel Required
- Continued Professional Development
- Job ID: HRD2298
- Category: Engineering
- Location: Brno, BM 62700 CZE
Honeywell is an equal opportunity employer. Qualified applicants will be considered without regard to age, race, creed, color, national origin, ancestry, marital status, affectional or sexual orientation, gender identity or expression, disability, nationality, sex, or veteran status.
Honeywell is an equal opportunity employer. Qualified applicants will be considered without regard to age, race, creed, color, national origin, ancestry, marital status, affectional or sexual orientation, gender identity or expression, disability, nationality, sex, religion, or veteran status.
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